1. Field of the Invention
The present invention is in the field of electronic circuits. The present invention is further in the field of analog integrated circuits. The implementation is not limited to a specific technology (i.e. CMOS or bipolar), and applies to either the invention as an individual component or to inclusion of the present invention within larger systems which may be combined into a larger integrated circuit.
The invention also falls within the field of DC voltage regulators and electronic power supplies, which convert energy from one DC level to another. These devices have been common in all electronic systems. More specifically, the invention falls into the class of voltage regulators referred to as series pass regulators or low dropout regulators, which convert a higher voltage to a lower voltage.
2. Brief Description of Related Art
Integrated circuit voltage regulators are common components which typically have an input terminal for receiving an input voltage, a common (ground) terminal, and an output terminal which supplies current to a load. The output terminal provides a substantially fixed voltage independent of the magnitude of the input voltage or the current provided to a load, provided that the input voltage is greater in magnitude than the desired output voltage.
Although many integrated circuit regulators provide this function only, it is common to provide additional functions in order to protect the circuitry and/or the load. It is usual to provide a mechanism to limit the maximum current the regulator will present the load. Many regulators also provide a means for disabling the output current, allowing an external enable/disable signal to determine whether the load will be powered. This is typical in large electronic systems with many individual functional blocks, where it may be desirable to selectively turn off those blocks to reduce power consumption when they are not required. Additional protections, such as over-temperature shutdown, are also common.
Available regulators can be characterized as either shunt regulators, which place a dissipative element in parallel with the load and control the shunted current to control the output voltage, or series pass regulators, which place a dissipative control element directly between the input voltage and the load. The latter technique has the advantage of being significantly more efficient than the shunt variety, and is the dominant approach used among integrated circuit regulators, and is the technique used in the present invention.
Among series pass regulators, there are two general classes. Conventional regulators use series pass elements which are unity gain followers (emitter followers or source followers), typically NPN or NMOS devices. This class of conventional regulator, in its integrated circuit form, is well described in “New Development in IC Voltage Regulatiors” (IEEE Journal of Solid States Circuit, vol. 6, no. 1 February 1971) by R. J. Wildlar. In order to drive the base or gate terminals, respectively, of these devices, the controlling signal must be higher in magnitude than the output voltage. This control signal requirement limits the “dropout voltage”, the difference between the input and output voltage of the regulator. In order to remove this limitation, a class of devices referred to as “LDO” or Low DropOut regulators was developed which used common emitter or common source output stages, typically PNP or PMOS transistors. The prior art circuit 1 using the PMOS transistor is shown in FIG. 1. Because the control signal (base or gate voltage) of these devices swings negative with respect to the emitter or source terminals, this control signal is not limited by the input voltage and it is possible to operate these devices with extremely small differences between input and output voltages.
Although the low dropout of the standard LDO circuits is very desirable, this architecture has some severe limitations in performance. The conventional regulator (using NPN or NMOS pass transistor) typically has much lower output impedance. The LDO typically requires a large capacitor at the output to maintain stable operations. Many LDOs are sensitive not only to the magnitude of capacitance across the load, but also to whether that capacitor looks like an ideal capacitor or whether it has a series resistive component at high frequencies. Selecting the wrong capacitor (too large or too small, too much series resistance or too little) can cause the LDO to oscillate.
The overall architecture of the series pass regulator is typically that of a feedback amplifier (as disclosed in the book “Analog Devices” in the chapter “Low-Dropout Regulators” by W. Jung). As shown in FIG. 1 such a regulator 1 includes an error amplifier A1 having an output connected to a gate terminal of the power transistor M1. A reference voltage generator V2 is amplified by a high gain feedback amplifier. As with all feedback systems, the performance is improved by increasing gain, but with a requirement that gain be rolled off at high frequencies in order to maintain the stability of the feedback loop. The mechanism for so limiting the high frequency gain is referred to as “compensation” and is of key importance in the design of all feedback systems.
In conventional regulator systems using unity gain follower outputs, the typical stabilization mechanism is to use a three stage amplifier. The first stage is a fixed transconductance, the second is a voltage gain stage, typically very high gain, which then drives a unity gain follower output stage. A feedback capacitor from the output or from the input to the follower, or both, is connected back to the output of the transconductance stage. This feedback around causes a dominant low frequency pole. This architecture is identical to the traditional feedback used in operational amplifiers.
Because this architecture has inherently low output impedance, which is further lowered by feedback, the system is relatively insensitive to loading. The reduction in feedback with increasing frequency can make the effective output impedance rise with frequency, causing it to look inductive. This inductive output impedance can, under certain circumstances, interact with capacitive loading to reduce the stability of the system, but the systems are generally very wideband and load insensitive.
The standard LDO is quite different in its frequency compensation. Typically the amplifier has two or three stages. An input stage compares a measure of the output voltage to the voltage reference. This stage may drive intervening stages, but eventually controls the common source/emitter output device. That final power stage provides voltage gain as a function of its transconductance and the load impedance (Av=gm*ZL). Since the load typically includes a capacitive component, that capacitor can be used to provide some of the gain reduction at high frequencies needed for stability. But typically the load capacitance is controlled by system requirements other than optimizing the stability of the LDO. It is therefore desirable to make the LDO stable over a wide range of capacitances.
It is not possible to use existing commercial LDOs without a large capacitive load (equal to or exceeding 1 uF). This results in the control loops of most LDOs being relatively slow. Since the LDO has very high output impedance without feedback, and a relatively low gain at high frequencies, it cannot maintain its output voltage in the presence of fast load changes.
To date, the primary approach to reduce the output capacitance sensitivity of the LDO has been to optimize the frequency compensation. Miranda (U.S. Pat. No. 5,686,821) and Brokaw (U.S. Pat. No. 5,631,598) use local capacitive feedback around the output devices and the driver stages to make these stages behave in a manner more similar to conventional output circuits using followers. Bakker et. al (U.S. Pat. No. 6,373,233) provided a somewhat similar solution, using a distributed RC network or its lumped equivalent around the output device alone.
Castelli et. al (U.S. Pat. No. 6,300,749) introduced a solution to add a mobile zero in the compensation circuit that is dependent on the second output pole of the LDO.
In all these cases the disadvantage is the need for an output capacitor to guarantee stability and adequate filtering of the output voltage.
There have been limited attempts to directly implement the older, faster control scheme in LDOs. One means of doing so is implemented in the UC385 regulator from Unitrode (now Texas Instruments). This regulator, element 2 in FIG. 2A, requires the introduction of a second higher voltage supply voltage V3 from which to run the control circuit. Power flows from the input supply V1 to the load with very low dropout voltage, but the gate/base drive of the pass transistor M2 is generated from the higher voltage supply. In principle, this second, higher voltage supply could be generated by the regulator 3 using a means such as a charge pump 4, as shown in FIG. 2B, but this would create unwanted noise and would delay startup until this required rail is generated. Such a regulator was introduced by Burr-Brown (now Texas Instruments), the REG101 and more recently by Philips, the SA57000-XX.
A more useful approach is the application of depletion mode power devices as pass transistors. Depletion mode devices are those where the turn-on threshold of the device is of a magnitude that zero control voltage allows the device to be conducting. JFETs and vacuum tube devices are inherently depletion mode devices, whereas bipolar transistors are inherently enhancement mode devices, inherently “off” with their control (base) pin held at the same potential as the emitter. MOSFETs can be made either enhancement or depletion by adjusting the surface concentration of the channel region. Most production CMOS processes include ion implantation steps to adjust the threshold of NMOS and PMOS devices to a desired threshold, typically a fraction of a volt. But an additional selective implant into devices destined to be depletion FETs can easily alter the threshold such that it is negative, forming depletion devices. This allows a standard CMOS process, with one additional mask step, to include depletion mode devices. Any process flow that builds enhancement mode MOSFETs can be modified slightly to provide depletion mode devices.
Wrathall et. al (U.S. Pat. No. 5,506,496) is an example of the use of depletion mode MOSFETs. There are several problems with the use of depletion mode pass devices, which are normally “on” and must have a negative voltage applied to their control terminal to turn them off. One problem is that under a condition of shorted load, where the output is at ground potential, the device will be on and cannot be turned off without the application of a negative gate voltage. Another potential problem with using depletion mode devices is that they are uncontrolled when voltage is initially applied. This causes the output voltage to be identical to the input voltage at start-up. Only after sufficient voltage exists to hold the gate below the source (output) by a voltage greater than the threshold voltage of the FET can any measure of control be imposed.
Wrathall's solution, to both problems, shown in FIG. 3, element 4, was a regulator 4 with PMOS device M3 as a switch in series with the source of the depletion mode MOSFET MD1. A switch control circuit 5 can selectively turn off PMOS device M3 in order to turn off current to the load. This implementation is not the ideal configuration, because in the condition of very low dropout voltage, it is necessary to fully enhance both NMOS and PMOS devices, i.e. maximizing the voltage from gate to source. When the regulated voltage is low, the PMOS device M3 in Wrathall cannot be fully enhanced. Similarly, by tying the source of the NMOS MD1 to the source of the PMOS M3, the Vgs which can be applied to the depletion NMOS is reduced resulting in increased total on resistance or bigger die area.
An earlier precedent for using “normally-on” devices comes from early regulator designs using thermionic devices (vacuum tube triodes and beam power pentodes). Vacuum tubes, like modern depletion FETs, were normally on with their control terminal (grid) held at the cathode voltage. By pulling the grid negative, the device could be turned off. A 1954 circuit for the HP 712B power supply, depicted in FIG. 4, shows very similar architecture to the conventional solid state series pass regulators discussed here. The gas discharge device U8 provides a voltage reference, a feedback amplifier comprising four triodes U1 through U4 compares this reference to a voltage divider taken from the output, and the amplifier drives a pass device U5, a beam power pentode. Note that as in the LDOs formed from enhancement devices in FIG. 2, this circuit requires a multiplicity of bias voltages, V5 and V6, in addition to the primary input voltage V4. Like the regulator using depletion MOSFET devices as in FIG. 3, this circuit required a switch SW1 that could keep the load disconnected during start-up, as the output voltage could rise to an uncontrolled high voltage before the active circuit could control it.
Accordingly, what is needed is a low dropout voltage regulator that combines the features of inherent stability, the ability to turn on and off very swiftly, the possibility to include a reliable means for limiting the output current and more importantly the capability to react extremely quickly to a change in load conditions. This would allow operation without the need for the output capacitor to filter the output voltage spikes and to provide stability to the control loop.